As the demand for smaller electronic products grows, manufacturers and others in the electronics industry continue to seek ways to reduce the size of the integrated circuits (ICs) used in the electronic products. In pursuit of that goal, three-dimensional (3D) type integrated circuit packaging techniques have been developed and used to produce three dimensional integrated circuits, or simply 3D ICs. Each 3D IC includes two or more chips stacked one on top of another and integrated both vertically and horizontally to generate a single circuit.
Because of the three dimensional structure of the 3D IC, the footprint of the stacked chips may be considerably smaller than the footprint of a conventional single layer chip. In other words, when viewed from above or below, the overall size of the stacked chips in the 3D IC may be smaller than the size of the conventional chip. However, due to the smaller footprint offered by the stacked chips in the 3D IC, it can be difficult for the 3D IC to contain all of the input/output (I/O) pads desired for a package.
Another way that the electronics industry is attempting to reduce the size of integrated circuits is by utilizing “flip chip” packaging. Flip chip microelectronic assembly is the direct electrical connection of face-down (hence, “flipped”) electronic components onto substrates, circuit boards, another chip, wafer or carriers using conductive solder bumps on the chip bond pads.
In a typical flip chip assembly process, integrated circuits are created on a wafer. Thereafter, pads on a top surface of the integrated circuits are metalized. Next, conductive solder balls (i.e., dots or bumps) are deposited on the pads and the integrated circuits on the wafer are separated or cut from each other to form individual chips. Thereafter, each chip is “flipped” over and positioned so that the solder balls of the chip are aligned with mating connectors on the underlying external circuitry. Finally, the solder balls are re-melted and the mounted chip is under-filled using an electrically-insulating adhesive in order to complete the conventional flip-chip package.
In some cases, one of the 3D ICs described above is utilized in the fabrication of a flip chip package. To ensure that such a 3D IC package has a pitch suitable for larger, thicker printed circuit boards (PBCs), an interposer, substrate, or other suitable structure may be attached to one side of the 3D IC in order to fan out (a.k.a., bond out) the I/O pad of the 3D IC.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.